One-time programmable memory unit cell

ABSTRACT

A one-time programmable memory unit cell includes a substrate comprising thereon a first active area and a second active area isolated from the first active area, a read select transistor disposed on the first active area, a data storage transistor disposed on the first active area and serially connected to the read select transistor, and a program select transistor disposed on the second active area. During read operation, the state “1” bit current is the transistor “on” current, while the state “0” bit current is the transistor “off” current.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. application Ser.No. 17/474,030, filed on Sep. 13, 2021, which is a continuationapplication of U.S. application Ser. No. 16/846,424, filed on Apr. 13,2020. The contents of these applications are incorporated herein byreference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present disclosure relates generally to the field of semiconductortechnology. More particularly, the present disclosure relates to athree-transistor (3T) one-time programmable (OTP) memory device.

2. Description of the Prior Art

As known in the art, non-volatile memory retains stored information evenafter power is removed from the non-volatile memory circuit. Somenon-volatile memory designs permit reprogramming, while other designsonly permit one-time programming. Thus, one form of non-volatile memoryis a One-Time Programmable (OTP) memory.

An OTP memory may contain an antifuse. An antifuse functions oppositelyto a fuse by initially being nonconductive. When programmed, theantifuse becomes conductive. To program an antifuse, a dielectric layersuch as an oxide is subjected to a high electric field to causedielectric breakdown or oxide rupture. After dielectric breakdown, aconductive path is formed through the dielectric and thereby makes theantifuse become conductive.

To read the memory cell, a current passing through the ruptured orunruptured oxide is typically required. However, some ruptured oxidescould be in a soft breakdown condition. The leakage current of the oxidein soft breakdown condition could be small. Therefore, a complicatesensing amplifier is often needed to compare the source side and drainside gate oxide leakage currents.

SUMMARY OF THE INVENTION

It is one objective of the present disclosure to provide athree-transistor (3T) one-time programmable (OTP) memory unit cell inorder to solve the deficiencies or shortcomings of the prior art.

One aspect of the invention provides a one-time programmable memory unitcell including a substrate comprising thereon a first active area and asecond active area isolated from the first active area, a read selecttransistor disposed on the first active area, a data storage transistordisposed on the first active area and serially connected to the readselect transistor, and a program select transistor disposed on thesecond active area. The read select transistor comprises a first gate, afirst gate dielectric layer between the first gate and the substrate, afirst drain region in the substrate on one side of the first gate, and afirst source region in the substrate on an opposing side of the firstgate.

The data storage transistor comprises a second gate, a second gatedielectric layer between the second gate and the substrate, a seconddrain region in the substrate on one side of the second gate, a secondsource region in the substrate on an opposing side of the second gate,and a channel region between the second drain region and the secondsource region. The second drain region merges with the first sourceregion of the read select transistor. The second gate comprises a maingate portion directly above the channel region, a first extension gateportion and a second extension gate portion on two opposite sidewalls ofthe main gate portion, respectively. The main gate portion, the firstextension gate portion and the second extension gate portion constitutea gate electrode of the data storage transistor. The second gatedielectric layer comprises a first portion between the drain region andthe first extension gate portion, a second portion between the channelregion and the main gate portion, and a third portion between the sourceregion and the second extension gate portion. The first portion and thethird portion are thinner than the second portion.

The program select transistor comprises a third gate, a third gatedielectric layer between the third gate and the substrate, a third drainregion in the substrate on one side of the third gate, and a thirdsource region in the substrate on the other side of the third gate. Thethird drain region is electrically coupled to the second gate of thedata storage transistor.

According to some embodiments, the one-time programmable memory unitcell further includes a first dielectric spacer and a second dielectricspacer on the first extension gate portion and the second extension gateportion, respectively.

According to some embodiments, the first dielectric spacer and thesecond dielectric spacer are situated directly on the first portion andthe third portion of the gate dielectric layer, respectively.

According to some embodiments, the first extension gate portion of thegate electrode is situated directly on the first portion of the gatedielectric layer and the second extension gate portion of the gateelectrode is situated directly on the third portion of the gatedielectric layer.

According to some embodiments, the one-time programmable memory unitcell further includes a first vertical PN junction disposed between thedrain region and the channel region and proximate to a top surface ofthe substrate, wherein the first vertical PN junction is situateddirectly underneath the main gate portion of the gate electrode; and asecond vertical PN junction disposed between the source region and thechannel region and proximate to the top surface of the substrate,wherein the second vertical PN junction is situated directly underneaththe main gate portion of the gate electrode.

According to some embodiments, the first gate, the second gate, and thethird gate comprise a single polysilicon layer or a metal gate.

According to some embodiments, the data storage transistor has agate-to-source/drain breakdown voltage lower than a gate-to-channelbreakdown voltage and a gated source/drain junction breakdown voltage.

According to some embodiments, the substrate is a P type siliconsubstrate, wherein the first drain region, the first source region, thesecond drain region, the second source region, the third drain region,and the third source region are N⁺ doping regions.

According to some embodiments, the program select transistor isconstructed on a triple well structure comprising a deep N well in the Ptype silicon substrate and a P well isolated from the P type siliconsubstrate by the deep N well.

According to some embodiments, the substrate comprises asilicon-on-insulator (SOI) substrate.

According to some embodiments, the third source region is electricallycoupled to ground.

According to some embodiments, the second active area is disposed inclose proximately to the first active area.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the embodiments, and are incorporated in and constitutea part of this specification. The drawings illustrate some of theembodiments and, together with the description, serve to explain theirprinciples. In the drawings:

FIG. 1 is a cross section of a semiconductor memory cell in accordancewith one embodiment of the invention;

FIG. 2 is a cross section of a semiconductor memory cell in accordancewith another embodiment of the invention, wherein a triple well isemployed;

FIG. 3 is a schematic diagram showing an exemplary semiconductor memoryarray composed of the semiconductor memory cell as depicted in FIG. 1 ;

FIG. 4 shows the selected memory cell for the program “1” operation inthe semiconductor memory array;

FIG. 5 is a cross section of the selected data storage transistor duringthe program “1” operation;

FIG. 6 shows the selected memory cell for the program “0” operation inthe semiconductor memory array;

FIG. 7 is a cross section of the selected data storage transistor duringthe program “0” operation;

FIG. 8 is a cross section of the data storage transistor with “1” stateduring read operation;

FIG. 9 is a cross section of the data storage transistor with “0” stateduring read operation; and

FIG. 10 to FIG. 17 are schematic diagrams showing an exemplary methodfor fabricating a MOS transistor having lower gate-to-source/drainbreakdown voltage according to one embodiment of the invention.

DETAILED DESCRIPTION

Advantages and features of embodiments may be understood more readily byreference to the following detailed description of preferred embodimentsand the accompanying drawings. Embodiments may, however, be embodied inmany different forms and should not be construed as being limited tothose set forth herein. Rather, these embodiments are provided so thatthis disclosure will be thorough and complete and will fully conveyexemplary implementations of embodiments to those skilled in the art, soembodiments will only be defined by the appended claims. Like referencenumerals refer to like elements throughout the specification.

Embodiments are described herein with reference to cross-sectionillustrations that are schematic illustrations of idealized embodiments(and intermediate structures). Thus, these embodiments should not beconstrued as limited to the particular shapes of regions illustratedherein but are to include deviations in shapes. For example, animplanted region illustrated as a rectangle will, typically, haverounded or curved features and/or a gradient of implant concentration atits edges rather than a binary change from implanted to non-implantedregion. Thus, the regions illustrated in the figures are schematic innature and their shapes are not intended to illustrate the actual shapeof a region of a device and are not intended to limit the scope of theembodiments.

It will be appreciated that although some conductivity types have beenused for illustrative purposes, the invention may be practiced withopposite conductivity types. For example, an NMOS transistor in oneembodiment may be replaced with a PMOS transistor in another embodimentwithout departing from the spirit and scope of the invention.

The present invention pertains to a MOS transistor having lowergate-to-source/drain breakdown voltage and OTP memory devices using suchMOS transistor. The OTP memory devices may comprise a plurality ofthree-transistor (3T) bit cell structures in the OTP memory array. TheOTP memory array utilizes the channel current, instead of ruptured orunruptured dielectric leakage current, for read operations. Thisinvention has a great advantage over the prior art because the state “1”bit current is the transistor “on” current that is consistently highwithout too much variation other than those caused by manufactureprocess fluctuation, while the state “0” bit current is the very smalltransistor “off” current.

One aspect of the invention provides a semiconductor device including atleast an OTP unit cell. A programming path for programming the OTP unitcell is different from a reading path for reading the OTP unit cell.According to some embodiments, the OTP unit cell comprises aprogrammable MOS transistor that is electrically programmed to “1” stateor “0” state. According to some embodiments, the programmable MOStransistor is programmed to the “1” state by rupturing a gate dielectriclayer between a gate and a drain of the MOS transistor. According tosome embodiments, the programmable MOS transistor is programmed to “0”state by rupturing the gate dielectric layer between the gate and asource of the MOS transistor. According to some embodiments, the gate ofthe programmable MOS transistor is switched between ground and floatingby a switching MOS transistor.

FIG. 1 is a cross section of a semiconductor memory cell (or OTP unitcell) in accordance with one embodiment of the invention. According toone embodiment of the invention, the illustrated semiconductor memorycell may be a 3T bit cell structure that is included in an OTP memoryarray. As shown in FIG. 1 , the semiconductor memory cell (or OTP unitcell) 1 comprises a read select transistor T_(RS) that is in seriesconnection with a data storage transistor T_(DS) for storing a digit “1”or a digital “0” data. The read select transistor Tits and the datastorage transistor T_(DS) may be constructed on the first active area101 that is isolated by a first trench isolation structure TI₁. Thefirst active area 101 may be defined on a semiconductor substrate 100having a first conductivity type, for example, P type. According to oneembodiment, for example, the semiconductor substrate 100 may be asilicon substrate or a silicon-on-insulator (SOI) substrate, but notlimited thereto.

The read select transistor Tits may be used to “select” a memory cellfor reading. According to one embodiment of the invention, the readselect transistor T_(RS) comprises a first gate G₁, a first gatedielectric layer OX₁ between the first gate G₁ and the semiconductorsubstrate 100, a first drain region D₁ in the semiconductor substrate100 on one side of the first gate G₁, and a first source region S₁ inthe semiconductor substrate 100 on the other side of the first gate G₁.According to one embodiment of the invention, the read select transistorTits may be an NMOS transistor, and the first drain region D₁ and thefirst source region S₁ may be N⁺ doping regions. The first gate G₁ maybe a single polysilicon (or single poly) layer or a metal gate.

According to one embodiment of the invention, the data storagetransistor T_(DS) comprises a second gate G₂, a second gate dielectriclayer OX₂ between the second gate G₂ and the semiconductor substrate100, a second drain region D₂ in the semiconductor substrate 100 on oneside of the second gate G₂, a second source region S₂ in thesemiconductor substrate 100 on the other side of the second gate G₂, anda channel region CH between the second drain region D₂ and the secondsource region S₂. According to one embodiment of the invention, the datastorage transistor T_(DS) may be an NMOS transistor, and the seconddrain region D₂ and the second source region S₂ may be N⁺ dopingregions. Likewise, the second gate G₂ may be a single polysilicon layeror a metal gate. Therefore, the read select transistor T_(RS) and thedata storage transistor T_(DS) constitute two serially connected NMOStransistors on the first active area 101. The N⁺ doping region 132between the first gate G₁ and the second gate G₂ in the semiconductorsubstrate 100 is commonly shared by the read select transistor T_(RS)and the data storage transistor T_(DS).

According to one embodiment of the invention, the portions 204 and 206of the second gate dielectric layer OX₂ that are situated directlybetween and the second gate G₂ and, respectively the second drain regionD₂ and the second source region S₂ are thinner than the portion 202 ofthe second gate dielectric layer OX₂ that is situated directly betweenthe channel region CH and the second gate G₂. Therefore, the second gatedielectric layer OX₂ has different thicknesses, thereby achieving alower gate-to-source/drain breakdown voltage of the data storagetransistor T_(DS).

Please refer to FIG. 16 for the detailed MOS transistor structure. FIG.16 is a cross section of an exemplary MOS transistor suited for the datastorage transistor having lower gate-to-source/drain breakdown voltageaccording to one embodiment of the invention, wherein like layers,elements or regions are designated by like numeral numbers or labels. Asshown in FIG. 16 , the MOS transistor T comprises a semiconductorsubstrate 100, a drain region 104 and a source region 106 in thesemiconductor substrate 100, a channel region CH between the drainregion 104 and the source region 106, a gate electrode 210 disposed onthe channel region CH, a gate dielectric layer 200 between the gateelectrode 210 and the semiconductor substrate 100. The gate dielectriclayer 200 has different thicknesses. According to one embodiment of theinvention, the portions 204 and 206 of the gate dielectric layer 200that are situated directly between the gate electrode 210 and,respectively, the drain region 104 and the source region 106 are thinnerthan the portion 202 of the gate dielectric layer 200 that is situateddirectly between the channel region CH and the gate electrode 210.

According to one embodiment of the invention, the gate electrode 210comprises a main gate portion 212 disposed directly above the channelregion CH and two extension gate portions 214 and 216 disposed on twoopposite sidewalls of the main gate portion 212. The extension gateportion 214 of the gate electrode 210 is situated directly on theportion 204 of the gate dielectric layer 200 and the extension gateportion 216 of the gate electrode 210 is situated directly on theportion 206 of the gate dielectric layer 200. The extension gate portion214 of the gate electrode 210 is in direct contact with the portion 204of the gate dielectric layer 200 and the extension gate portion 216 ofthe gate electrode 210 is in direct contact with the portion 206 of thegate dielectric layer 200. According to one embodiment of the invention,the main gate portion 212, the extension gate portion 214, and theextension gate portion 216 of the gate electrode 210 may be composed ofdoped polysilicon, silicide, or metal, but is not limited thereto.

The outer surface of the extension gate portion 214 of the gateelectrode 210 is covered with a dielectric spacer 224 and the outersurface of the extension gate portion 216 of the gate electrode 210 iscovered with a dielectric spacer 226. According to one embodiment of theinvention, for example, the dielectric spacers 224 and 226 may comprisesilicon nitride, silicon oxynitride or silicon oxide, but is not limitedthereto. According to one embodiment of the invention, an end surface204 a of the portion 204 may be aligned with an outer surface of thedielectric spacer 224 and an end surface 206 a of the portion 206 may bealigned with an outer surface of the dielectric spacer 226. According toone embodiment of the invention, the dielectric spacer 224 may besituated on the portion 204 of the gate dielectric layer 200 and thedielectric spacer 226 may be situated on the portion 206 of the gatedielectric layer 200.

According to one embodiment of the invention, the MOS transistor Tfurther comprises a self-aligned silicide (or salicide) layer 232 on thegate electrode 210, a salicide layer 234 on the drain region 104, and asalicide layer 236 on the source region 106. According to one embodimentof the invention, salicide layers 232, 234 and 236 may comprise NiSi,CoSi, TiSi, or WSi, but is not limited thereto. According to oneembodiment of the invention, the salicide layer 234 is contiguous withthe end surface 204 a of the portion 204, and the salicide layer 236 iscontiguous with the end surface 206 a of the portion 206.

According to one embodiment of the invention, the vertical PN junctions104 a and 106 a, which are proximate to the top surface of thesemiconductor substrate 100 and are between the channel region CH and,respectively, the drain region 104 and the source region 106 aresituated directly underneath the main gate portion 212 of the gateelectrode 210. By providing such configuration, a higher gatedsource/drain junction breakdown voltage can be provided. According toone embodiment of the invention, the MOS transistor T has agate-to-source/drain breakdown voltage that is lower than agate-to-channel breakdown voltage and the gated source/drain junctionbreakdown voltage.

Adverting to FIG. 1 , the semiconductor memory cell 1 further comprisesa program select transistor T_(PS) that is used to “select” a memorycell for programming. The program select transistor T_(PS) isconstructed on the second active area 102 that is isolated by a secondtrench isolation structure TI 2. The second active area 102 may bedisposed in close proximately to the first active area 101. According toone embodiment of the invention, the program select transistor T_(PS)comprises a third gate G₃, a third gate dielectric layer OX₃ between thethird gate G₃ and the semiconductor substrate 100, a third drain regionD₃ in the semiconductor substrate 100 on one side of the third gate G₃,and a third source region S₃ in the semiconductor substrate 100 on theother side of the third gate G₃. The third drain region D₃ iselectrically coupled to the second gate G₂.

According to one embodiment of the invention, the program selecttransistor T_(PS) may be an NMOS transistor, and the third drain regionD₃ and the third source region S₃ may be N⁺ doping regions. Likewise,the third gate G₃ may be a single polysilicon layer or a metal gate.

In another embodiment, as shown in FIG. 2 , the semiconductor memorycell 1 a comprising the read select transistor T_(RS), the data storagetransistor T_(DS), and the program select transistor T_(PS) may beconstructed on a triple well structure comprising a deep N well 110 inthe P type semiconductor substrate (P Substrate) 100 and a P well 120isolated from the P type semiconductor substrate 100 by the deep N well110. During program or read operations, the P well may be biased to apredetermined P well voltage through a P well pickup region (not shownin this figure). It is understood that the illustrated transistors inFIG. 1 and FIG. 2 may further comprise other elements such as spacers onsidewalls of the gates or lightly doped drain (LDD) regions merged withthe heavily doped source/drain regions, which are not explicitly shownin the figures for the sake of simplicity.

According to one embodiment of the invention, during operation, thefirst drain region D₁ is electrically coupled to a bit line voltageV_(BL), the first source region S₁ and the second drain region D₂ (i.e.,the N⁺ doping region 132) are electrically floating, the second sourceregion S₂ is electrically coupled to a source line voltage V_(SL), thethird source region S₃ is electrically coupled to ground (GND), thefirst gate G₁ is electrically coupled to a read select voltage V_(Rsel),and the third gate G₃ is electrically coupled to a program selectvoltage V_(Psel).

FIG. 3 is a diagram showing an exemplary semiconductor memory arraycomposed of the semiconductor memory cell as depicted in FIG. 1 . It isunderstood that although only a 2×3 cell array are shown in FIG. 3 , thesemiconductor memory array may be an arbitrary N by M array comprisingmemory cells arranged in N rows and M columns, where N and M arearbitrary numbers. For example, the memory cell MC₀ at the crosspoint ofthe row Ro and the column Co comprises the read select transistorT_(RS), the data storage transistor T_(DS), and the program selecttransistor T_(PS) as described in FIG. 1 . The first drain region D₁ ofthe read select transistor T_(RS) is electrically connected to a bitline BL₀, the second source region S₂ of the data storage transistorT_(DS) is electrically connected to a source line SL₀, the first gate G₁of the read select transistor T_(RS) is electrically connected to a readselect line R_(sel0), and the third gate G₃ of the program selecttransistor T_(PS) is electrically connected to a program select lineP_(sel0).

Please refer to Table 1 below, FIG. 4 , FIG. 5 , and briefly to FIG. 1and FIG. 2 . FIG. 4 shows the selected memory cell (or bit unit) of thesemiconductor memory array. FIG. 5 is a cross section of the selecteddata storage transistor T_(DS) during the program “1” operation. Table 1shows exemplary bias conditions for programming digital “1” to theselected semiconductor memory cell in FIG. 4 .

TABLE 1 Program “1” Condition Terminal Bias Voltage Selected P_(Sel),V_(Psel) 1-3 V Unselected P_(Sel) 0 V Selected R_(Sel), V_(Rsel) 3-10 VSelected BL, V_(BL) 3-10 V or Ramp up from 0 V till breakdown UnselectedBL 0 V or Floating V_(SL) 0 V or Floating V_(PW) 0 V or FloatingV_(PSub)/V_(DNW) 0 V or Floating

According to one embodiment of the invention, to program the selectedbit unit to “1” state, the following bias conditions may be implemented:

-   -   (i) a program select voltage V_(Psel) of about 1-3V is applied        to the selected program select line P_(sel) (selected P_(sel))        to turn on the program select transistor T_(PS);    -   (ii) a high enough read select voltage V_(Rsel) ranging between,        for example, 3-10V may be applied to the selected read select        line R_(sel)(selected R_(sel));    -   (iii) all the unselected program select lines P_(sel)        (unselected P_(sel)) and unselected read select lines R_(sel)        (unselected R_(sel)) are connected to ground GND (or 0 V);    -   (iv) the semiconductor substrate 100 (e.g., P Substrate) is        usually connected to ground (V_(PSub)=0 V), and for the triple        well structures as set forth in FIG. 2 , the deep N well 110 is        connected to ground (V_(DNW)=0V) while the P well 120 may be        floating or connected to ground (V_(PW)=0V or floating);    -   (v) all the source lines SL and unselected bit lines BL are        floating or connected to ground (0V); and    -   (vi) the selected bit line voltage V_(BL) is ramped up,        preferred to be through a current limiter to prevent overloading        the bit line voltage supply circuit, until a sudden increase in        current A and a sudden drop in voltage across the second gate        dielectric layer OX₂, indicating dielectric breakdown B, in FIG.        5 , directly above the second drain region D₂ of the selected        data storage transistor T_(DS).

Alternatively, the dielectric breakdown B may be caused by simplyapplying a pre-set bit line voltage V_(BL) that is higher than gatedielectric breakdown voltage (i.e., portion 204 OX₂ breakdown voltage),to the selected bit line, which is also preferred to be done through acurrent limiter to prevent overloading the bit line voltage supplycircuit.

It is one technical feature of the invention that to write digital “1”,only the thinner portion 204 of the second gate dielectric layer OX₂that is adjacent to the second drain region D₂ (i.e. drain sidedielectric) is ruptured, while the portion 206 of the second gatedielectric layer OX₂ that is adjacent to the second source region S₂(i.e. source side dielectric) and the portion 202 directly over thechannel region CH (i.e. channel dielectric) are remained intact.

Preferably, the data storage transistor T_(DS) may have source junctionbreakdown voltage and drain junction breakdown voltage, which are higherthan the gate dielectric breakdown voltage of the data storagetransistor. However, this is not necessary for the embodiments withtriple well structures as described in FIG. 2 . Further, the gatedielectric breakdown voltage and the junction breakdown voltage of theread select transistor T_(RS) are both higher than the gate dielectricbreakdown voltage of the data storage transistor T_(DS). This can beachieved by using thicker gate dielectric or cascoding two transistorsfor the read select transistor T_(RS).

Please refer to Table 2 below, FIG. 6 , FIG. 7 , and briefly to FIG. 1and FIG. 2 . FIG. 6 shows the selected memory cell (or bit unit) in thesemiconductor memory array. FIG. 7 is a cross section of the selecteddata storage transistor T_(DS) during the program “0” operation. Table 2shows exemplary bias conditions for programming digital “0” to theselected semiconductor memory cell in FIG. 6 .

TABLE 2 Program “0” Condition Terminal Bias Voltage Selected P_(Sel),V_(Psel) 1-3 V All R_(Sel) 0 V or don't care Unselected P_(Sel), 0 VSelected SL, V_(SL) 3-10 V or Ramp up from 0 V till breakdown UnselectedSL 0 V or Floating All BL, V_(BL) 0 V or Floating P-Well, V_(PW) 0 V orFloating Others, V_(PSub)/V_(DNW) 0 V or Floating

According to one embodiment of the invention, to program the selectedbit unit to “0” state, the following bias conditions may be implemented:

-   -   (i) a program select voltage V_(Psel) of about 1-3V is applied        to the selected program select line P_(sel) (selected P_(sel))        to turn on the program select transistor T_(PS);    -   (ii) all the unselected program select lines P_(sel) (unselected        P_(sel)) are connected to ground (or 0 V);    -   (iii) all the read select lines R_(sel) are connected to 0 V or        don't care;    -   (iv) the semiconductor substrate 100 (e.g., P Substrate) is        usually connected to ground (0 V), and for the triple well        structures as set forth in FIG. 2 , the deep N well 110 is        connected to ground (V_(DNW)=0 V) while the P well 120 may be        floating or connected to ground (V_(PW)=0 V or floating);    -   (v) all the bit lines BL and unselected source lines SL are        floating or connected to ground; and    -   (vi) the selected source line voltage V_(SL) is ramped up,        preferred to be through a current limiter to prevent overloading        the source line voltage supply circuit, until a sudden increase        in current A and a sudden drop in voltage across the second gate        dielectric layer OX₂, indicating dielectric breakdown B, in FIG.        7 , directly on the second source region S₂ of the selected data        storage transistor T_(DS).

Alternatively, the dielectric breakdown B may be caused by simplyapplying a pre-set source line voltage V_(SL) that is higher than gatedielectric breakdown voltage (i.e., portion 206 of OX₂ breakdownvoltage), to the selected source line, which is also preferred to bethrough a current limiter to prevent overloading the source line voltagesupply circuit.

It is another technical feature of the invention that to write digital“0”, only the portion 206 of the second gate dielectric layer OX₂ thatis adjacent to the second source region S₂ (i.e. source side dielectric)is ruptured, while the portion 204 of the second gate dielectric layerOX₂ that is adjacent to the second drain region D₂ (i.e. drain sidedielectric) and the portion 202 directly over the channel region CH(i.e. channel dielectric) are remained intact.

Please refer to Table 3 below, FIG. 8 and FIG. 9 . FIG. 8 is a crosssection of the data storage transistor T_(DS) with “1” state during readoperation. FIG. 9 is a cross section of the data storage transistorT_(DS) with “0” state during read operation. Table 3 shows exemplarybias conditions for reading data storage transistor T_(DS).

To read a memory cell, the following exemplary bias conditions may beimplemented:

-   -   (i) all the program select lines P sel are connected to ground        (0 V) to turn off all program select transistors T_(PS) so that        all the second gates G₂ of the data storage transistors T_(DS)        are isolated from the outside bias. Therefore, voltage of the        second gate G₂ of the data storage transistors T_(DS) is the        same as that of second drain region D₂ if the dielectric        breakdown B, caused during the programming procedure, is on the        drain side, and the same as that of second source region S₂ if        the dielectric breakdown B is on the source side;    -   (ii) a read select voltage V_(Rsel) of about 1-3V is applied to        the selected read select lines R_(sel) so that drain of the        selected data storage transistors T_(DS) is connected to the        selected bit line BL to which a bit line voltage V_(BL) of        0.5-2V is applied; and    -   (iii) all the other terminals are connected to ground (0 V).

TABLE 3 Read Bias Condition Terminal Bias Voltage All P_(Sel) 0 VSelected R_(Sel) 1-3 V Unselected R_(Sel), 0 V Selected BL 0.5-2 VUnselected BL 0 V or Floating All SL 0 V P-Well 0 V Others 0 V

Under the aforesaid read bias conditions, the data storage transistorsT_(DS) has a high channel current CL if the dielectric breakdown B is onthe drain side because the gate voltage is high, same as the voltageapplied to the second drain region D₂, and the data storage transistorsT_(DS) (“1” state) is turned on, as shown in FIG. 8 . On the other hand,for the data storage transistors T_(DS) in “0” state, there is nochannel current (or only an insignificant amount of off-current) becausethe voltage coupled to the second gate G₂ is low, same as the voltageapplied to the second source region S₂, and the data storage transistorsT_(DS) (“0” state) is turned off, as shown in FIG. 9 . Therefore, theread current path is not through the ruptured dielectric, but is throughthe channel region CH of the data storage transistor T_(DS).

According to some embodiments, all the isolated second gates G₂ of thedata storage transistors T_(DS) may be pre-charged by turning on allread select transistors T_(R) simultaneously and applying 0.5-2V to allbit lines and 0 V to all source line for a short period of time (e.g., 3ms) prior to reading the entire OTP memory array. This can prevent thosesoft breakdown bits from errors due to slow charging.

FIG. 10 to FIG. 17 are schematic diagrams showing an exemplary methodfor fabricating a MOS transistor having lower gate-to-source/drainbreakdown voltage according to one embodiment of the invention, whereinlike layers, elements or regions are designated by like numeral numbersor labels.

As shown in FIG. 10 , a semiconductor substrate 100 such as a P typesilicon substrate is provided. A gate dielectric layer 200 such assilicon dioxide (SiO₂), silicon oxynitride (SiON) or hafnium dioxide(HfO₂), or the combination of two or more is deposited on thesemiconductor substrate 100. According to one embodiment, the gatedielectric layer 200 may have a thickness of about 2-20 nm, but is notlimited thereto. A first conductive layer 210 a such as N-dopedpolysilicon, silicide or metal is then deposited on the gate dielectriclayer 200. For example, the first conductive layer 210 a is an N-dopedpolysilicon layer. According to one embodiment, the first conductivelayer 210 a may have a thickness of about 80-200 nm, but is not limitedthereto. Optionally, a cap nitride layer 230 may be deposited on thefirst conductive layer 210 a. For example, the cap nitride layer 230 maybe a silicon nitride layer and may have a thickness of about 5-10 nm.

It will be appreciated that although some conductivity types have beenused for illustrative purposes, the invention may be practiced withopposite conductivity types.

Subsequently, as shown in FIG. 11 , a photoresist pattern PR is formedon the cap nitride layer 230 to define gate area. An anisotropic etchingprocess 500 is then performed to remove the cap nitride layer 230 andthe first conductive layer 210 a not covered by the photoresist patternPR, thereby forming a main gate portion 212. At this point, the gatedielectric layer 200 is substantially not etched.

As shown in FIG. 12 , the remaining photoresist pattern PR is removed.An ion implantation process 600 is then performed to implant N typedopants into the semiconductor substrate 100, thereby forming N⁺ drainregion 104 and N⁺ source region 106. According to one embodiment, the N⁺drain region 104 and N⁺ source region 106 may be formed with gradedjunction, which may be formed by using, for example, doubly diffusedmethod, for higher junction breakdown voltage.

As shown in FIG. 13 , an etching process is performed to remove an upperportion of the gate dielectric layer 200, thereby forming a thinnerportions 204 and 206 on the N⁺ drain region 104 and N⁺ source region106, respectively. The portions 204 and 206 may be thinned down tothickness of 30-70% of the original thickness. According to oneembodiment, the etching process may be a wet etching process, but is notlimited thereto. It is understood that in some embodiments the ionimplantation process 600 in FIG. 12 may be performed after gatedielectric thinning down.

As shown in FIG. 14 , a second conductive layer 210 b such as N-dopedpolysilicon, silicide or metal is deposited on the semiconductorsubstrate 100. The second conductive layer 210 b conformally covers themain gate portion 212 and the thinner portions 204 and 206. The secondconductive layer 210 b is in direct contact with the sidewalls of themain gate portion 212. For example, the second conductive layer 210 b isan N-doped polysilicon layer. According to one embodiment, the secondconductive layer 210 b may have a thickness of about 20-100 nm.

As shown in FIG. 15 , an anisotropic etching process 700 is thenperformed to etch the second conductive layer 210 b, thereby formingextension gate portions 214 and 216 on the opposite sidewalls of themain gate portion 212. The extension gate portion 214 is situateddirectly on the portion 204 of the gate dielectric layer 200 and theextension gate portion 216 of the gate electrode 210 is situateddirectly on the portion 206 of the gate dielectric layer 200.

As shown in FIG. 16 , the cap nitride layer 230 is removed, optionally.After the removal of the cap nitride layer 230, the top surface of themain gate portion 212 is revealed. Subsequently, a dielectric spacer 224and a dielectric spacer 226 are formed on the gate dielectric layer 200and the extension gate portions 214 and 216 of the gate electrode 210,respectively. Removal of cap nitride layer 230 can also be achievedduring formation of spacer 224 and spacer 226. The formation of thedielectric spacers 224 and 226 may involve conformal deposition of aspacer material layer and anisotropic etch of the spacer material layer.In some embodiments, the cap nitride layer 230 is not removed prior tothe conformal deposition of the spacer material layer, and the capnitride layer 230 can be removed during anisotropic etch of the spacermaterial layer.

The outer surface of the extension gate portion 214 of the gateelectrode 210 is covered with the dielectric spacer 224 and the outersurface of the extension gate portion 216 of the gate electrode 210 iscovered with the dielectric spacer 226. According to one embodiment ofthe invention, for example, the dielectric spacers 224 and 226 maycomprise silicon nitride, silicon oxynitride or silicon oxide, but isnot limited thereto. According to one embodiment of the invention, anend surface 204 a of the portion 204 is aligned with an outer surface ofthe dielectric spacer 224 and an end surface 206 a of the portion 206 isaligned with an outer surface of the dielectric spacer 226.

A self-aligned silicidation process is then performed to form a salicidelayer 232 on the gate electrode 210, a salicide layer 234 on the drainregion 104, and a salicide layer 236 on the source region 106. Accordingto one embodiment of the invention, salicide layers 232, 234 and 236 maycomprise NiSi, CoSi, TiSi, or WSi, but is not limited thereto. Accordingto one embodiment of the invention, the salicide layer 234 is contiguouswith the end surface 204 a of the portion 204, and the salicide layer236 is contiguous with the end surface 206 a of the portion 206.According to one embodiment of the invention, the salicide layer 234 isnot in direct contact with the dielectric spacer 224, and salicide layer236 is not in direct contact with the dielectric spacer 226.

According to one embodiment of the invention, the vertical PN junctions104 a and 106 a proximate to the top surface of the semiconductorsubstrate 100 are situated directly underneath the main gate portion 212of the gate electrode 210. By providing such configuration, a highergated source/drain junction breakdown voltage can be provided. Accordingto one embodiment of the invention, the MOS transistor T has agate-to-source/drain breakdown voltage that is lower than agate-to-channel breakdown voltage and the gated source/drain junctionbreakdown voltage.

As shown in FIG. 17 , an interlayer dielectric (ILD) layer 240 is thendeposited on the semiconductor substrate 100. The ILD layer 240 coversthe MOS transistor T. Subsequently, a contact plug 244 and a contactplug 246 may be formed in the ILD layer 240. An interconnect structure254 and an interconnect structure 256 may be formed on the ILD layer240. The interconnect structure 254 is electrically connected to thedrain region 104 through the contact plug 244. The interconnectstructure 256 is electrically connected to the source region 106 throughthe contact plug 246.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A one-time programmable memory unit cell,comprising: a substrate comprising thereon a first active area and asecond active area isolated from the first active area; a read selecttransistor disposed on the first active area, wherein the read selecttransistor comprises a first gate, a first gate dielectric layer betweenthe first gate and the substrate, a first drain region in the substrateon one side of the first gate, and a first source region in thesubstrate on an opposing side of the first gate; a data storagetransistor disposed on the first active area and serially connected tothe read select transistor, wherein the data storage transistorcomprises a second gate, a second gate dielectric layer between thesecond gate and the substrate, a second drain region in the substrate onone side of the second gate, a second source region in the substrate onan opposing side of the second gate, and a channel region between thesecond drain region and the second source region, wherein the seconddrain region merges with the first source region of the read selecttransistor, wherein the second gate comprises a main gate portiondirectly above the channel region, a first extension gate portion and asecond extension gate portion on two opposite sidewalls of the main gateportion, respectively, wherein the main gate portion, the firstextension gate portion and the second extension gate portion constitutea gate electrode of the data storage transistor, and wherein the secondgate dielectric layer comprises a first portion between the drain regionand the first extension gate portion, a second portion between thechannel region and the main gate portion, and a third portion betweenthe source region and the second extension gate portion, wherein thefirst portion and the third portion are thinner than the second portion;and a program select transistor disposed on the second active area,wherein the program select transistor comprises a third gate, a thirdgate dielectric layer between the third gate and the substrate, a thirddrain region in the substrate on one side of the third gate, and a thirdsource region in the substrate on the other side of the third gate,wherein the third drain region is electrically coupled to the secondgate of the data storage transistor.
 2. The one-time programmable memoryunit cell according to claim 1 further comprising: a first dielectricspacer and a second dielectric spacer on the first extension gateportion and the second extension gate portion, respectively.
 3. Theone-time programmable memory unit cell according to claim 2, wherein thefirst dielectric spacer and the second dielectric spacer are situateddirectly on the first portion and the third portion of the gatedielectric layer, respectively.
 4. The one-time programmable memory unitcell according to claim 1, wherein the first extension gate portion ofthe gate electrode is situated directly on the first portion of the gatedielectric layer and the second extension gate portion of the gateelectrode is situated directly on the third portion of the gatedielectric layer.
 5. The one-time programmable memory unit cellaccording to claim 1 further comprising: a first vertical PN junctiondisposed between the drain region and the channel region and proximateto a top surface of the substrate, wherein the first vertical PNjunction is situated directly underneath the main gate portion of thegate electrode; and a second vertical PN junction disposed between thesource region and the channel region and proximate to the top surface ofthe substrate, wherein the second vertical PN junction is situateddirectly underneath the main gate portion of the gate electrode.
 6. Theone-time programmable memory unit cell according to claim 1, wherein thefirst gate, the second gate, and the third gate comprise a singlepolysilicon layer or a metal gate.
 7. The one-time programmable memoryunit cell according to claim 1, wherein the data storage transistor hasa gate-to-source/drain breakdown voltage lower than a gate-to-channelbreakdown voltage and a gated source/drain junction breakdown voltage.8. The one-time programmable memory unit cell according to claim 1,wherein the substrate is a P type silicon substrate, wherein the firstdrain region, the first source region, the second drain region, thesecond source region, the third drain region, and the third sourceregion are N⁺ doping regions.
 9. The one-time programmable memory unitcell according to claim 8, wherein the program select transistor isconstructed on a triple well structure comprising a deep N well in the Ptype silicon substrate and a P well isolated from the P type siliconsubstrate by the deep N well.
 10. The one-time programmable memory unitcell according to claim 1, wherein the substrate comprises asilicon-on-insulator (SOI) substrate.
 11. The one-time programmablememory unit cell according to claim 1, wherein the third source regionis electrically coupled to ground.
 12. The one-time programmable memoryunit cell according to claim 1, wherein the second active area isdisposed in close proximately to the first active area.